A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS

Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
2013 IEEE Journal of Solid-State Circuits  
This paper presents a 5-bit 1.25-GS/s folding flash ADC. The prototype achieves a folding factor of four with a capacitive folding technique that only consumes dynamic power. Incorporated with various calibration schemes, folding errors and the comparator's threshold inaccuracies are corrected, thus allowing a low input capacitance of 80 fF. The design is fabricated using 65-nm digital CMOS technology and occupies 0.007 mm . The maximum DNL and INL post calibration are 0.67 and 0.47 LSB,
more » ... ively. Measurement results show that the ADC can achieve 1.25 GS/s at 1-V supply with a total power consumption of 595 W. In addition, it exhibits a mean ENOB of 4.8b at dc among ten chips, which yields an FoM of 17 fJ/conversion-step.
doi:10.1109/jssc.2013.2264617 fatcat:l5jdjz2mgvfbjc5xtkmcxngjqa