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A 32kb 9T SRAM with PVT-tracking read margin enhancement for ultra-low voltage operation
2015
2015 IEEE International Symposium on Circuits and Systems (ISCAS)
Diminishing bitline sensing margin at low voltage condition is one of the most challenging design obstacles for reliable SRAM implementation in nano-scale CMOS technologies. This paper presents a self-biased design technique that improves the bitline sensing margin during the read operation by sourcing a current which is the same as the total leakage along each bitline. It is able to automatically track changes in supply voltage, operating temperature and die-to-die process variations.
doi:10.1109/iscas.2015.7169206
dblp:conf/iscas/DoYK15
fatcat:2vhwqlpe3baivbf54e3vvg3bue