A 32kb 9T SRAM with PVT-tracking read margin enhancement for ultra-low voltage operation

Anh-Tuan Do, Kiat-Seng Yeo, Tony Tae-Hyoung Kim
2015 2015 IEEE International Symposium on Circuits and Systems (ISCAS)  
Diminishing bitline sensing margin at low voltage condition is one of the most challenging design obstacles for reliable SRAM implementation in nano-scale CMOS technologies. This paper presents a self-biased design technique that improves the bitline sensing margin during the read operation by sourcing a current which is the same as the total leakage along each bitline. It is able to automatically track changes in supply voltage, operating temperature and die-to-die process variations.
more » ... re, a 9T SRAM cell is utilized to ensure that bitline leakage is data-independent. Simulation and measurement results using 65 nm CMOS process show that the proposed technique enlarge the bitline swing over a wide range operating temperature and operates successfully down to the supply voltage of 0.18 V.
doi:10.1109/iscas.2015.7169206 dblp:conf/iscas/DoYK15 fatcat:2vhwqlpe3baivbf54e3vvg3bue