A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
Design and Implementation of High Performance MAC Unit
unpublished
Preserved Fulltext
A design of high performance 64 bit Multiplier-and-Accumulator (MAC) is implemented in this paper. MAC unit performs important operation in many of the digital signal processing (DSP) applications. The multiplier is designed using modified Wallace multiplier and the adder is done with carry save adder. The total design is coded with Synthesize and simulate by verilog-HDL. Keywords-Modified Wallace multiplier, Carry save adder, multiplier and accumulator (MAC).
fatcat:eyw6lymw3bcthfw6v7glx3flvu