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Using Barrier Elision to Improve Transactional Code Generation
2022
ACM Transactions on Architecture and Code Optimization (TACO)
With chip manufacturers such as Intel, IBM and ARM offering native support for transactional memory in their instruction set architectures, memory transactions are on the verge of being considered a genuine application tool rather than just an interesting research topic. Despite this recent increase in popularity on the hardware side of transactional memory (HTM), software support for transactional memory (STM) is still scarce and the only compiler with transactional support currently
doi:10.1145/3533318
fatcat:s4jfcnwz3zcfnjfkqppviuel7a