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Relying on a recently developed gate-level information assurance scheme, we formally analyze the security of design-for-test (DFT) scan chains, the industrial standard testing methods for fabricated chips and, for the first time, formally prove that a circuit with scan chain inserted can violate security properties. The same security assessment method is then applied to a built-in-self-test (BIST) structure where it is shown that even BIST structures can cause security vulnerabilities. Todoi:10.1109/isvlsi.2014.54 dblp:conf/isvlsi/Jin14 fatcat:t3ub7g7p35hd3izto6ua4e3zxy