A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Efficient On-Chip Idle Cache Utilization Technique in Chip Multi-Processor Architecture
칩 멀티 프로세서 구조에서 온칩 유휴 캐시의 효과적인 활용 방안
2013
Journal of the Korea Society of Computer and Information
칩 멀티 프로세서 구조에서 온칩 유휴 캐시의 효과적인 활용 방안
Preserved Fulltext
Recently, although the number of cores on a chip multi-processor increases, multi-programming or multi-threaded programming techniques to utilize the whole cores are still insufficient. Therefore, there inevitably exist some idle cores which are not working. This results in a waste of the caches, so-called idle caches which are dedicated to those idle cores. In this research, we propose a methodology to exploit idle caches effectively as victim caches of on-chip memory resource. In simulation
doi:10.9708/jksci.2013.18.10.013
fatcat:dtsrh6lpsbddponomungyf2jvq