Dominator-based partitioning for delay optimization

David Bañeres, Jordi Cortadella, Mike Kishinevsky
2006 Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06  
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techniques are not always suitable for delay and area logic optimizations. The paper presents an approach that uses a dominator-based partitioning and conventional logic synthesis techniques for delay optimization of large networks. The calculation of dominators is crucial to find topologically ordered clusters suitable for
more » ... logic restructuring. As a result, a scalable and efficient strategy for delay optimization is proposed and evaluated, showing tangible improvements with respect to existing techniques. A comparison with a standard mincut-based partitioning technique is also presented.
doi:10.1145/1127908.1127927 dblp:conf/glvlsi/BaneresCK06 fatcat:m6bwtwhizfgxjek4hilbqb24v4