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Dominator-based partitioning for delay optimization
Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techniques are not always suitable for delay and area logic optimizations. The paper presents an approach that uses a dominator-based partitioning and conventional logic synthesis techniques for delay optimization of large networks. The calculation of dominators is crucial to find topologically ordered clusters suitable fordoi:10.1145/1127908.1127927 dblp:conf/glvlsi/BaneresCK06 fatcat:m6bwtwhizfgxjek4hilbqb24v4