Polyhedral-based data reuse optimization for configurable computing

Louis-Noel Pouchet, Peng Zhang, P. Sadayappan, Jason Cong
2013 Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '13  
Many applications, such as medical imaging, generate intensive data traffic between the FPGA and off-chip memory. Significant improvements in the execution time can be achieved with effective utilization of on-chip (scratchpad) memories, associated with careful software-based data reuse and communication scheduling techniques. We present a fully automated C-to-FPGA framework to address this problem. Our framework effectively implements data reuse through aggressive loop transformation-based
more » ... ram restructuring. In addition, our proposed framework automatically implements critical optimizations for performance such as task-level parallelization, loop pipelining, and data prefetching. We leverage the power and expressiveness of the polyhedral compilation model to develop a multi-objective optimization system for off-chip communications management. Our technique can satisfy hardware resource constraints (scratchpad size) while still aggressively exploiting data reuse. Our approach can also be used to reduce the on-chip buffer size subject to bandwidth constraint. We also implement a fast design space exploration technique for effective optimization of program performance using the Xilinx high-level synthesis tool.
doi:10.1145/2435264.2435273 dblp:conf/fpga/PouchetZSC13 fatcat:zaashltg3bcw7pasjfjh6lep3e