Floorplan Design and Yield Enhancement of 3-D Integrated Circuits [report]

Rajeev Nain
2000 unpublished
The semiconductor industry has witnessed aggressive scaling of transistors following Moore's law, and has harnessed its benefits in terms of speed, density, and die size in the past several decades. At present transistor count has crossed one billion per chip, and transistor delay has been reduced to picoseconds range. However, the aggressive scaling has slowed down in deep submicron technology because of several challenges in VLSI design and manufacturability. Due to increasing power,
more » ... ce, cost of fabrication, challenges in lithography, and other financial bottlenecks beyond 28nm, the industry has begun to look for alternative solutions. This has led to the current focus of the industry on stacked three-dim~nsional (3-D) ICs. Three-dimensional integrated circuits, in which multiple device layers are stacked vertically, are an alternative solution to interconnect related·p~oblems. One of the main objectives of 3-D ICs is to replace longer interconnects by shorter wires and vias. Thus it reduces total wirelength, signal delay, buffer ~ount, and power consumption. In addition, 3-D ICs are more suitable for system-on-chip (SOC) design, in which heterogeneous technologies can be fabricated independently in different device layers prior to 3-D stacking. Thus different families of circuits such as logic, processor, memory, analog/RF circuits, sensors, optical I/ Os etc. can be integrated in the ACKNOWLEDGMENTS I would like to thank my advisor Malgorzata Chrzanowska-J eske, whose encouragement, supervision and support from the preliminary to concluding level enabled me to pursue the research. I sincerely thank all the members of my dissertation committee for their participation during various stages of my academic progress. My special thanks to Prof. Robert Daasch for providing useful feedback on 3-D IC yield work during my seminar presentation. Furthermore, I wish to thank my colleague Rehman Ashraf for the insightful discussions during the research work related to 3-D IC yield. My special thanks to Darcy Kennc;dy and Melissa Sutherland for their help during proof reading of my research articles, and this dissertation. Finally I would like to thank my family for their endless support and love. Without their support, the completion of this work wo~d not have been possible.
doi:10.15760/etd.2804 fatcat:kp4fd3recnc3dexj43747w5p4m