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Latch-Based Performance Optimization for FPGAs
2011
2011 21st International Conference on Field Programmable Logic and Applications
We explore using pulsed latches for timing optimization -a first in the FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (non-50%) duty cycle. We exploit existing functionality within commercial FPGA chips to implement latch-based optimizations that do not have the power or area drawbacks associated with other timing optimization approaches, such as clock skew and retiming. We propose an algorithm that iteratively replaces certain flip-flops in a
doi:10.1109/fpl.2011.21
dblp:conf/fpl/TengA11
fatcat:tz5tpxkxfvf2tcmyt6bfsvqhxi