A spur-free fractional-N ΣΔ PLL for GSM applications: linear model and simulations

M. Cassia, P. Shah, E. Bruun
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.  
A new PLL topology and a new simplified linear model are presented The new EA fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a SampleJHold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.
doi:10.1109/iscas.2003.1205751 dblp:conf/iscas/CassiaSB03 fatcat:bryi7ee6s5hqjphaspj52bqoiq