Compact delay modeling of latch-based threshold logic gates

M. Padure, S. Cotofana, C. Dan, S. Vassiliadis, M. Bodea
Proceedings. International Semiconductor Conference  
In this paper we propose a new compact static delay model for latch-based CMOS Threshold logic gates. The particular effects captured by the model are: the dependency of the delay on threshold (data) values and the dependency of the delay vs. capacitive loading. The model parameters were extracted from several Threshold logic gate setups and the delay predicted by the model for a computer arithmetic basic circuit fully agree with circuit simulations. W
doi:10.1109/smicnd.2002.1105858 fatcat:ntc4t5c27vgp3le7sdutvkk74y