A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications]

S.M. Louwsma, E.J.M. van Tuijl, M. Vertregt, P.C.S. Scholtens, B. Nauta
Proceedings of the 30th European Solid-State Circuits Conference  
A 1.6 GS/s Track and Hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR f o r a 950 MHzfull scale input signal is 50 dE. Phase alignment is better than 2 p s and aperture uncertainty is less than 0.8 p s (RMS). The chip includes two Analog to Digital Converters and a Switching Matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm2 excluding the AD Converters. The chip is
more » ... ters. The chip is made in a 0 . 1 2 p a . 1.2 V CMOS Process. Power consumption of the interleaving T/H circuit is 32 mW
doi:10.1109/esscir.2004.1356688 fatcat:5vhlaigp65gzjhos4tkusx3dty