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A Wide Input Range, 95.4% Power Efficiency DC-DC Buck Converter with a Phase-Locked Loop in 0.18 ㎛ BCD
2016
Journal of Power Electronics (JPE)
This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM
doi:10.6113/jpe.2016.16.6.2024
fatcat:awiyhpfyffg5dj567ude22362u