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Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs
2008
2008 Design, Automation and Test in Europe
Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testing of multiple cores of a system-on-chip (SoC) in parallel during WLTBI leads to constantly-varying device power during the duration of the test. This power variation adversely affects predictions of temperature and the time required for burn-in. We present a test-scheduling technique for WLTBI of core-based SoCs, where the
doi:10.1109/date.2008.4484925
dblp:conf/date/BahukudumbiCK08
fatcat:irwksuhr7reqpmqpnc2vc2biwa