Exploiting Bit-Level Write Patterns to Reduce Energy Consumption in Hybrid Cache Architecture

Juhee Choi, Heemin Park
2021 IEICE Electronics Express  
A hybrid cache architecture (HCA) is introduced to alleviate the drawbacks of non-volatile memory (NVM) technologies. Although researchers have offered meaningful ways to conserve energy, little attention has been paid to focus on write counts that are non-uniformly spread over a cache line. We propose a novel HCA to reduce the NVM write counts by exploiting bit-level write patterns. The data array is refined to separately store bits in the cache line to the NVM region and the SRAM region. As a result, 20.1% of energy is saved over prior works.
doi:10.1587/elex.18.20210327 fatcat:ra4agxjiljhs7cobjbq7cwwrva