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A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models
Computer Design (ICCD '99), IEEE International Conference on
This paper presents a system-level Network-on-Chip modeling framework that integrates transaction-level model and analytical wire model for design space exploration. It enables the analysis of influence of physical wire properties on the system performance and power dissipation in early design stages. SystemC provides the infrastructure to integrate transaction-level model and low-level models. By utilizing approximate timing, different temporal granularity can be used, leading to fastdoi:10.1109/iccd.2006.4380845 dblp:conf/iccd/XiZ06 fatcat:jf3ryylg25brpmgqubp4sv2i74