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Lecture Notes in Computer Science
The arrival of best-effort hardware transactional memory (TM) creates a challenge for designers of transactional memory runtime libraries. On the one hand, using hardware TM can dramatically reduce the latency of transactions. On the other, it is critical to create a fall-back path to handle the cases where hardware TM cannot complete a transaction, and this path ought to be scalable and reasonably fair to all transactions. Additionally, while the hardwareaccelerated system is likely to havedoi:10.1007/978-3-662-48653-5_15 fatcat:kjdyxo25sjgnfkfq7omrr332xi