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Many critical design trade-offs of the Class-E power amplifier (e.g power efficiency) are influenced by the switch onresistance and the value of dc-feed drain inductance. In literature, the time-domain mathematical analyses of the Class-E power amplifier with finite dc-feed inductance assume zero switch onresistance in order to alleviate the mathematical difficulties; resulting in non-optimum designs. We present analytical design equations in this paper for Class-E power amplifier taking intodoi:10.1109/iscas.2007.378758 dblp:conf/iscas/AcarAN07 fatcat:rfbricxqanfprc5yovy4zm3ixe