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Bounds modelling and compiler optimizations for superscalar performance tuning
1999
Journal of systems architecture
We consider the¯oating point microarchitecture support in RISC superscalar processors. We brie¯y review the fundamental performance trade-os in the design of such microarchitecutres. We propose a simple, yet eective bounds model to deduce the"best-case" loop performance limits for these processors. We compare these bounds to simulated and real performance measurements. From this study, we identify several loop tuning opportunities. In particular, we illustrate the use of this analysis in
doi:10.1016/s1383-7621(98)00053-8
fatcat:rvqysiv5gzb6zmbrvffoqcgafi