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The paper describes work at the Polytechnic of Huddersfield on SERC/DTI research project IED 2/1/2121 conducted in collaboration with GEC-Plessey Semiconductors, Wolfson Microelectronics, and UMIST. The aim of the work is to develop generic testing strategies for mixed-signal (mixed analogue and digital) integrated circuits. The paper proposes a test structure for mixed-signal ICs, and details the development of a test technique and fault model for the analogue circuit cells encountered indoi:10.1049/ip-g-2.1992.0038 fatcat:ac6strpeibacnf3r27y653c7jm