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The test set size is a highly important factor in the post-production test of circuits. A high pattern count in the test set leads to long test application time and exorbitant test costs. We propose a new test generation approach which has the ability to reduce the test set size significantly. In contrast to previous SAT-based ATPG techniques which were focused on dealing with hard single faults, the proposed approach employs the robustness of SAT-solvers to primarily push test compaction.doi:10.1109/ddecs.2012.6219063 dblp:conf/ddecs/EggersglussKGHD12 fatcat:4zpcdgwokfb3tgo2turwginwby