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The shared last-level caches in CMPs play an important role in improving application performance and reducing off-chip memory bandwidth requirements. In order to use LLCs more efficiently, recent research has shown that changing the re-reference prediction on cache insertions and cache hits can significantly improve cache performance. A fundamental challenge, however, is how to best predict the re-reference pattern of an incoming cache line. This paper shows that cache performance can bedoi:10.1145/2155620.2155671 dblp:conf/micro/WuJHMSE11 fatcat:mafbit5x7bbcpnq6i2zahkuwpe