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Formal Verification of SystemC Designs Using a Petri-Net Based Representation
2006
Proceedings of the Design Automation & Test in Europe Conference
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is then used for model checking of properties expressed in a timed temporal logic. The approach is particularly suitable for, but not restricted to, models at a high level of abstraction, such as transaction-level. The efficiency of the approach is illustrated by experiments.
doi:10.1109/date.2006.244076
dblp:conf/date/KarlssonEP06
fatcat:dpsklngn5fdjhn7mpg4dg6o7iu