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In this paper divide by N prescaler counter is discuss. Instead of using conventional counter design technologies, a decision logic circuit is needed to generate predictable counting states. This circuit can be design by using transmission gate logic as a basic design cell. An initial module generates predictable counting states for higher significant bit modules through the state look-ahead path. In order to attain high operating frequency a high speed parallel counter is presented. In ourdoi:10.17148/ijarcce.2017.6616 fatcat:gxvqcksfu5fjdkdsi5jup4rudm