Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems

J. M. Ludden, W. Roesner, G. M. Heiling, J. R. Reysa, J. R. Jackson, B.-L. Chu, M. L. Behm, J. R. Baumgartner, R. D. Peterson, J. Abdulhafiz, W. E. Bucy, J. H. Klaus (+13 others)
<span title="">2002</span> <i title="IBM"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cr766v23pncdhc7hmikak4m7pi" style="color: black;">IBM Journal of Research and Development</a> </i> &nbsp;
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems This paper describes the methods and simulation techniques used to verify the microarchitecture design and functional performance of the IBM POWER4 processor and the POWER4-based Regatta system. The approach was hierarchical, based on but considerably expanding the practice used for verification of the CMOS-based IBM S/390 Parallel Enterprise Server TM G4. For POWER4, verification began at the abstract,
more &raquo; ... evel design phase and continued throughout the designer and unit levels, the multi-unit level, and finally the multiple-chip system level. The abstract (high-level design) phase permitted early validation of the POWER4 processor design prior to its commitment to HDL. The designer and unit-level stages focused on ensuring the correctness of the microarchitectural components. Multi-unitlevel verification, performed on storage and I/O components as well as on the processor, confirmed architectural compliance for each of the chips and subsystems. Finally, system-level verification tested multiprocessor coherence and system-level function, including processor-to-I/O communication and validation of multiple hardware configurations. In parallel with design and functional validation, verification of reliability functions, performance, and degraded configurations was also performed at most of the levels in the hierarchy. PowerPC RISC architecture PowerPC [2] is traditionally recognized as a reducedinstruction-set computer (RISC) architecture which adheres to a basic philosophy of keeping the hardware design simple. The intent is to place more responsibility on software than is done by traditional complexinstruction-set computer (CISC) architectures such as the IBM S/390* or the Intel x86. Despite this notion of keeping things simple, the architecture presents many challenges to the verification process: • The ordering of performance-critical instructions is often the responsibility of software and is accomplished by inserting context-synchronizing instructions into the instruction stream at the proper point. This increases the difficulty of verification because it is possible to create illegal instruction streams which lead to unpredictable hardware behavior. • A weakly consistent memory model is assumed; the order in which loads and stores execute with respect to each other and to accesses by other processors can vary significantly. In general, loads and stores can execute out of order with respect to other processors and one another (on the same processor), provided that all accesses are consistent and properly aligned accesses are atomic. • Address translation responsibility is shared between software and hardware. PowerPC translation uses a twostep approach which separates the "effective-to-real" translation mechanism into an "effective-to-virtual" address translation and then a "virtual-to-real" address translation. Sim farm A massive simulation infrastructure was required to simulate a processor and system of this size and sophistication. The infrastructure begins with the "sim farm," which consists of thousands of IBM pSeries* workstations and servers running the AIX operating system in Austin, Texas, and Rochester, Minnesota. The network is connected using 100Mb Ethernet at each site. The processing capability enabled us to average over a billion cycles per day.
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