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Performance driven resynthesis by exploiting retiming-induced state register equivalence
1999
Proceedings of the conference on Design, automation and test in Europe - DATE '99
This paper presents a retiming and resynthesis technique for cycle-time minimization of sequential circuits circuits with feedbacks (finite state machines). Operating on the delay critical paths of the circuit, we perform a set of controlled local retimings of registers across fanout stems and logic gates, followed by local node simplifications. We guide the retiming of registers across fanout stems to induce equivalence relations among them, which are exploited for subsequent logic
doi:10.1145/307418.307579
fatcat:bir22zdvnfafneqc4v3jlajesi