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Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications
2008
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
This paper presents the design of a low-power programmable pseudorandom word generator (PRWG) and a low-noise clock multiplier unit (CMU) for high-speed SerDes applications. The PRWG is capable of producing test patterns with sequence length of 2 7 1, 2 10 1, 2 15 1, 2 23 1, and 2 31 1 b according to CCITT recommendations, and the random word is 16-bit wide. High-speed and low-power operations of the PRWG are achieved by parallel feedback techniques. The measured jitter of the CMU is only 3.56
doi:10.1109/tcsi.2008.916507
fatcat:5ifcpj2safa7xco77rt4cafn24