Effect of TSV fabrication technology on power distribution in 3D ICs

Suhas M. Satheesh, Emre Salman
2013 Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI - GLSVLSI '13  
The design implications of two distinct through silicon via (TSV) fabrication methods (via-first and via-last) have been investigated for power delivery in a 3D system. Different geometry, connectivity, and filling materials have been considered to develop equivalent electrical models for both via-first and via-last based power distribution networks. Based on these models, a valid design space has been developed where power supply noise is satisfied and physical area overhead is minimized.
more » ... is minimized. Under constant power supply noise, a via-last based power network occupies 7.5% less area. However, in addition to causing routing blockages, a via-last based power network exhibits high sensitivity to design parameters due to a high quality factor. Alternatively, a via-first based power network requires a large number of TSVs, but exhibits relatively more predictable behavior due to a lower quality factor (higher damping).
doi:10.1145/2483028.2483111 dblp:conf/glvlsi/SatheeshS13 fatcat:4gktwndt3jdyxdgcw3d6tuhjvm