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Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is the dominant power component in second-level (L2) caches. This paper presents two architectural techniques to utilize leakage reduction circuits in L2 caches. They primarily target the leakage in the peripheral circuitry of an L2 cache and as such have to be able to cope with longer delays. One technique exploits the fact that processor activity decreases significantly after an L2 cache missdoi:10.1109/iccd.2007.4601907 dblp:conf/iccd/HomayounV07 fatcat:llcrpba5ojewjlwpvkk5zitsu4