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Homogeneous manycore processors are emerging for terascale computation. Effective defect tolerance techniques are essential to improve the yield of such complex integrated circuits. In this paper, we propose to achieve fault tolerance by employing redundancy at the core-level instead of at the microarchitecture-level. When faulty cores existing on-chip in this architecture, how to reconfigure the processor with the most effective topology is a relevant research problem. We present noveldoi:10.1109/date.2008.4484787 dblp:conf/date/ZhangHXL08 fatcat:zypetvtp4bhm7hofolkieln4ae