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An energy-efficient and scalable eDRAM-based register file architecture for GPGPU
2013
SIGARCH Computer Architecture News
The heavily-threaded data processing demands of streaming multiprocessors (SM) in a GPGPU require a large register file (RF). The fast increasing size of the RF makes the area cost and power consumption unaffordable for traditional S-RAM designs in the future technologies. In this paper, we propose to use embedded-DRAM (eDRAM) as an alternative in future GPGPUs. Compared with SRAM, eDRAM provides higher density and lower leakage power. However, the limited data retention time in eDRAM poses new
doi:10.1145/2508148.2485952
fatcat:nbaghtk2rvhfri6wkpah4t27ta