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Previous studies have shown that the interconnection network of a Chip-Multiprocessor (CMP) has significant impact on both overall performance and energy consumption. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth and power characteristics. In this work, we present a proposal for performance-and energy-efficient message management in tiled CMPs that combines both address compression with a heterogeneous interconnect. Our proposal consists of applyingdoi:10.1109/icpp.2008.33 dblp:conf/icpp/FloresAA08 fatcat:icsnub6qoba2fapgvr2lbe425a