Accelerating Multiprocessor Simulation with a Memory Timestamp Record

K.C. Barr, H. Pan, M. Zhang, K. Asanovic
2005 IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005.  
We introduce a fast and accurate technique for initializing the directory and cache state of a multiprocessor system based on a novel software structure called the memory timestamp record (MTR). The MTR is a versatile, compressed snapshot of memory reference patterns which can be rapidly updated during fast-forwarded simulation, or stored as part of a checkpoint. We evaluate MTR using a full-system simulation of a directory-based cachecoherent multiprocessor running a range of multithreaded
more » ... loads. Both MTR and a multiprocessor version of functional fast-forwarding (FFW) make similar performance estimates, usually within 15% of our detailed model. In addition to other benefits, we show that MTR has up to a 1.45× speedup over FFW, and a 7.7× speedup over our detailed baseline.
doi:10.1109/ispass.2005.1430560 dblp:conf/ispass/BarrPZA05 fatcat:bnsfxw65kjhorof2fdxvmw7wiu