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Accelerating Multiprocessor Simulation with a Memory Timestamp Record
2005
IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005.
We introduce a fast and accurate technique for initializing the directory and cache state of a multiprocessor system based on a novel software structure called the memory timestamp record (MTR). The MTR is a versatile, compressed snapshot of memory reference patterns which can be rapidly updated during fast-forwarded simulation, or stored as part of a checkpoint. We evaluate MTR using a full-system simulation of a directory-based cachecoherent multiprocessor running a range of multithreaded
doi:10.1109/ispass.2005.1430560
dblp:conf/ispass/BarrPZA05
fatcat:bnsfxw65kjhorof2fdxvmw7wiu