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Towards an Efficient Memory Architecture for Video Decoding Systems
2012
2012 Brazilian Symposium on Computing System Engineering
Multimedia applications are known to use large amounts of memory. The video modules need also high throughput memory port for coding and decoding high resolution video sequences. The design of a multimedia Systemon-Chip (SoC) could implement embedded block RAMs but it is much more cost-effective to use a single external memory at the expense of a multichannel memory controller. This paper presents the design and implementation of an efficient memory hierarchy for a Set-Top Box (STB) SoC with a
doi:10.1109/sbesc.2012.45
dblp:conf/sbesc/BonattoNSS12
fatcat:bb4ssi5eyver7kqqaibo7hn25e