Simultaneous Escape Routing (SER) is escaping of circuit pins simultaneously from inside two or more pin arrays. This is comparatively difficult as compared to routing in a single array and has not been addressed by previous studies. The increase in pin array complexity has made the manual SER in PCBs a very inefficient and tedious task and there surely is need for the automated routing algorithms. In this work we propose network flow based optimal algorithm that uses integer linear program to

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... olve SER problem and area routing problem in two stages. In the first stage, pins are escaped to the boundaries of pin arrays simultaneously. These escaped pins are connected with each other in the second stage. The proposed algorithm is tested for different benchmark sizes of grids and the results show that it is not only better in terms of routability but also outperforms existing state of the art algorithms in terms of time consumption. The existing algorithms either fails to achieve higher routability or have larger time complexities. Whereas the proposed algorithm achieves 99.9% routability and it is also independent of grid topology and component pin arrangement which shows the superiority of proposed algorithm over the existing algorithms. PeerJ Comput. Sci. reviewing PDF | (ABSTRACT 10 Simultaneous Escape Routing (SER) is escaping of circuit pins simultaneously from inside two or more pin arrays. This is comparatively difficult as compared to routing in a single array and has not been addressed by previous studies. The increase in pin array complexity has made the manual SER in PCBs a very inefficient and tedious task and there surely is need for the automated routing algorithms. In this work we propose network flow based optimal algorithm that uses integer linear program to solve simultaneous escape routing problem and area routing problem in two stages. In the first stage, pins are escaped to the boundaries of pin arrays simultaneously. These escaped pins are connected with each other in the second stage. We tested the proposed algorithm for different benchmark sizes of grids and the results show that it is not only better in terms of routability but also outperforms existing state of the art algorithms in terms of time consumption. The existing algorithms either fails to achieve higher routability or have larger time complexities. Whereas the proposed algorithm achieves 99.9% routability and it is also independent of grid topology and component pin arrangement which shows the superiority of proposed algorithm over the existing state of art algorithms. ) are also inflicted upon PCB routing. 35 These constraints combined together with the increasing density of the packages impose a bigger 36 challenge on the PCB routing and therefore, take manual routing out of the consideration. This is where 37 the automated routers come into the play for the solution of these issues and are currently used for the 38 PCB routing. Automated routers help solve various PCB routing problems including escape routing and 39 the area routing problem. The escaping of pins to the array boundary is known as escape routing and 40 connecting these escaped pins in the intermediate area is known as area routing. Escape routing and 41 area routing together play very important role in PCB routing. The pins on boundary of a pin array can 42 easily be escaped and connected to their corresponding pins by keeping the via constraint in mind. But 43 there are many pins which are inside the pin array and they cannot be connected directly and have to be 44 escaped towards the boundary first which is known as escape routing problem. Escape routing problem is 45 PeerJ Comput. Sci. reviewing PDF | (one of the critical challenges in the PCB design because the modern ICs have a pin array that contains 46 a large number of pins. The studies show that escape routing has three different types Yan and Wong 47 93 We finally discuss results before concluding the work. 94 RELATED WORK 95 PCBs are widely used for the modern age electric circuits fabrication. The design of a PCB plays a vital 96 role in the performance of electric circuits. The ever evolving technology has not only reduced the size of 97 2/15 PeerJ Comput. Sci. reviewing PDF | (148 simultaneously and minimize the net ordering mismatch. There are some studies in the literature that have 149 proposed a simultaneous pin assignment Xiang et al. (2001); Wang et al. (1991), Ozdal et al. Ozdal and 150 Wong (2004, 2006) propose a methodology to escape the pins to boundaries in such a way that crossings 151 are minimized in the intermediate area. Polynomial time algorithm is used for smaller problems and 152 3/15 PeerJ Comput. Sci. reviewing PDF | (