Energy-efficient signal processing via algorithmic noise-tolerance

Rajamohana Hegde, Naresh R. Shanbhag
<span title="">1999</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qcoemsk4lfgznflartfnzb5rhy" style="color: black;">Proceedings of the 1999 international symposium on Low power electronics and design - ISLPED &#39;99</a> </i> &nbsp;
In this paper, we propose a framework for low-energy digital signal processing (DSP) where the supply voltage is scaled beyond the critical voltage required to match the critical path delay to the throughput. This deliberate introduction of input-dependent errors leads to degradation in the algorithmic performance, which is compensated for via algorithmic noise-tolerance (ANT) schemes. The resulting setup that comprises of the DSP architecture operating at sub-critical voltage and the error
more &raquo; ... rol scheme is referred to as soft DSP. It is shown that technology scaling renders the proposed scheme more effective as the delay penalty suffered due to voltage scaling reduces due to short channel effects. The effectiveness of the proposed scheme is also enhanced when arithmetic units with a higher "delay-imbalance" are employed. A prediction based error-control scheme is proposed to enhance the performance of the filtering algorithm in presence of errors due to soft computations. For a frequency selective filter, it is shown that the proposed scheme provides 60%;81% reduction in energy dissipation for filter bandwidths up to 0:5 (where 2 corresponds to the sampling frequency fs) over that achieved via conventional voltage scaling, with a maximum of 0:5dB degradation in the output signal-to-noise ratio (S NR o). It is also shown that the proposed algorithmic noise-tolerance schemes can be used to improve the performance of DSP algorithms in presence of bit-error rates of upto 10 ;3 due to deep submicron (DSM) noise.
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