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Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM based FPGA
[article]
2018
arXiv
pre-print
Efficient low complexity error correcting code(ECC) is considered as an effective technique for mitigation of multi-bit upset (MBU) in the configuration memory(CM)of static random access memory (SRAM) based Field Programmable Gate Array (FPGA) devices. Traditional multi-bit ECCs have large overhead and complex decoding circuit to correct adjacent multibit error. In this work, we propose a simple multi-bit ECC which uses Secure Hash Algorithm for error detection and parity based two dimensional
arXiv:1810.09661v1
fatcat:tr7kolhvovg7lnbaesasb3mxcm