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Timing speculation is a promising technique for improving microprocessor yield, in field reliability, and energy efficiency. Previous evaluations of the energy efficiency benefits of timing speculation have either been based on code compiled for a traditional target  -a processor that produces no errors, or code that relies on additional hardware support  . In this paper, we advocate that binaries for timing speculative processors should be optimized differently than those fordoi:10.1145/2228360.2228602 dblp:conf/dac/SartoriK12 fatcat:anfejuhrcrfl7agwqpiykggskm