Abstrac -This paper proposes a method for reducing the fault testing times for digital VLSI circuits by duplicating individual functional flip-flops. The reduction in testing time is due to better signal testability and fewer mutual conflicts between faults occurring in the logic paths of VLSI circuits. Proposed here is an algorithm for selecting flip-flops to be duplicated based on a search for logic paths with the largest number of signal sources, which was used in the design of built-in test

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... tools for a number of custom-designed units and system-on-a-chip designs. The results showed a decrease in test time by an average of 14.4 % with hardware costs not exceeding 1.2 % of the total VLSI chip area.