S. Agarwala, T. Anderson, A. Hill, M.D. Ales, R. Damodaran, P. Wiley, S. Mullinnix, J. Leach, A. Lell, M. Gill, A. Rajagopal, A. Chachad (+8 others)
2002 IEEE Journal of Solid-State Circuits  
A 600-MHz VLIW digital signal processor (DSP) delivers 4800 MIPS, 2400 (16 b) or 4800 (8 b) million multiply accumulates (MMACs) at 0.3 mW/MMAC (16 b). The chip has 64M transistors and dissipates 718 mW at 600 MHz and 1.2 V, and 200 mW at 300 MHZ and 0.9 V. It has an eight-way VLIW DSP core, a two-level memory system, and an I/O bandwidth of 2.4 GB/s. The chip integrates a c64X DSP core with Viterbi and turbo decoders. Architectural and circuit design approaches to achieve high performance and
more » ... gh performance and low power using a semi-custom standard cell methodology, while maintaining backward compatibility, are described. The chip is implemented in a 0.13-m CMOS process with six layers of copper interconnect. Index Terms-Cache, digital signal processor (DSP), DMA, signal integrity, turbo decoder, Viterbi decoder, VLIW. 0018-9200/02$17.00 © 2002 IEEE Sanjive Agarwala received the B.S.E.E. degree from Panjab University, India, in 1984 and the M.S.C.S. degree from Southern Methodist University, Dallas, TX, in 1990. He joined the Texas Instruments (TI) R&D Lab, Dallas, in 1986, working on the development of circuit synthesis and timing analysis tools. Subsequently, he led the memory hierarchy development on two generations of x86 microprocessors at TI. In 1997, he led the design and development of the C62x DSP followed by the development of the high-performance C64x DSP at TI. He is currently a TI Fellow and Design Manager of the C64x design group at TI. He holds six U.S. patents.
doi:10.1109/jssc.2002.803954 fatcat:zhz5fsoz55d4pivgn63zyce4hq