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Compact Modeling of 0.35 micron SOI CMOS Technology Node for 4 K DC Operation using Verilog-A
[article]
2010
arXiv
pre-print
Compact modeling of MOSFETs from a 0.35 micron SOI technology node operating at 4 K is presented. The Verilog-A language is used to modify device equations for BSIM models and more accurately reproduce measured DC behavior, which is not possible with the standard BSIM model set. The Verilog-A approach also allows the embedding of nonlinear length, width and bias effects into BSIM calculated curves beyond those that can be achieved by the use of different BSIM parameter sets. Nonlinear
arXiv:1001.3353v1
fatcat:r5qgnnrzhjflhb4bqc3to2lvmm