Specification and validation of control-intensive IC's in hopCP

V. Akella, G. Gopalakrishnan
1994 IEEE Transactions on Software Engineering  
Control intensive ICs pose a signi cant c hallenge to the users of formal methods in designing hardware. These ICs have t o s u p p o r t a w i d e v ariety of requirements including synchronous and asynchronous operations, polling and interrupt-driven modes of operation, multiple concurrent threads of execution, non-trivial computational requirements, and programmability. I n t h i s p a p e r , w e illustrate the use of formal methods in the design of a control intensive IC called the \Intel
more » ... 251" Universal Synchronous/Asynchronous Receiver/Transmitter (USART), using our hardware description language'hopCP'. A feature of hopCP is that it supports communication via asynchronous ports in addition to synchronous message passing. Asynchronous ports are distributed shared variables writable by exactly one process. We show the usefulness of this combination of communication constructs. We outline algorithms to determine safe usages of asynchronous ports, and also to discover other static properties of the speci cation. We discuss a compiledcode concurrent functional simulator called CFSIM, a s w ell as the use of concurrent testers for driving CFSIM. The use of a semantically well speci ed and simple language, and the associated analysis/simulation tools helps conquer the complexity of specifying and validating control intensive I C s .
doi:10.1109/32.295890 fatcat:jx2r2i5hkves7fhqysfuub3x2q