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A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC
[article]
2016
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I would also like to thank Dr. Michael Orshansky for being this report's reader and for being patient throughout. In addition, I would like to thank Miguel Gandara, my mentor for this project who has helped me relentlessly at any time of the day. He not only taught me about new and innovative design techniques but also helped me remain calm whenever we got stuck on a problem. Lastly, I would like to thank my family and friends without whose constant support this would not have been possible.
doi:10.15781/t24f1n25b
fatcat:fx6bkgfaojef5j72bkfedcnifi