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An Interleaved Full Nyquist High-Speed DAC Technique
IEEE Journal of Solid-State Circuits
A 9-bit 11GS/s DAC is presented that achieves an SFDR of more than 50dB across Nyquist and IM3 below -50dBc across Nyquist. The DAC uses a two-times interleaved architecture to suppress spurs that typically limit DAC performance. Despite requiring two current-steering DACs for the interleaved architecture, the relative low demands on performance of these sub-DACs imply that they can be implemented in an area and power efficient way. Together with a quad-switching architecture to decreasedoi:10.1109/jssc.2014.2387946 fatcat:foxe74sa75hodioxee7tkgkk4y