Bandwidth optimized motion compensation hardware design for H.264/AVC HDTV decoder

Chuan-Yung Tsai, Tung-Chien Chen, To-Wei Chen, Liang-Gee Chen
2005 48th Midwest Symposium on Circuits and Systems, 2005.  
Design of H.264/AVC motion compensation (MC) is very challenging through the high memory bandwidth and low hardware utilization caused by the new functionalities of variable block size and 6-tap interpolation filter. In this paper, the Vertically Integrated Double Z (VIDZ) schedule, and Interpolation Window Reuse (IWR) and Interpolation Window Classification (IWC) bandwidth reduction schemes are proposed to keep the MC highly utilized and save 60-80% memory bandwidth. The hardware of proposed
more » ... dware of proposed MC is implemented at 120MHz with 47K logic gates and can support 2048×1024 30fps H.264/AVC HDTV decoder with less than 200MB/s memory bandwidth. 0-7803-9197-7/05/$20.00
doi:10.1109/mwscas.2005.1594322 fatcat:zuyy7o7sx5dglecwn7gvkwptyy