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2011 IEEE 9th International Symposium on Intelligent Systems and Informatics
In this paper several hardware implementations of decision trees (axis-parallel, oblique and non-linear) based on the concept of universal node and sequence of universal nodes are presented. Proposed hardware architectures are suitable for the implementation in both Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC). Proposed architectures can be easily customized in order to fit a wide variety of application requirements, fulfilling their role as generaldoi:10.1109/sisy.2011.6034358 fatcat:d5t6loeag5ewvoh5kux3w5tek4