Integrating formal verification and high-level processor pipeline synthesis

Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien L. Lu
2011 2011 IEEE 9th Symposium on Application Specific Processors (SASP)  
When a processor implementation is synthesized from a specification using an automatic framework, this implementation still should be verified against its specification to ensure the automatic framework introduced no error. This paper presents our effort in integrating fully automated formal verification with a high-level processor pipeline synthesis framework. As an integral part of the pipeline synthesis, our framework also emits SMV models for checking the functional equivalence between the
more » ... utput pipelined processor implementation and its input non-pipelined specification. Well known compositional model checking techniques are automatically applied to curtail state explosion during model checking. The paper reports case studies of applying this integrated framework to synthesize and formally verify pipelined RISC and CISC processors.
doi:10.1109/sasp.2011.5941073 dblp:conf/sasp/NurvitadhiHKL11 fatcat:xrnee2lta5eexexddvf5ndr2di