An Sdl (Simple Description Language) Analyzer

Robert Borrmann
2001 Annual Conference Proceedings   unpublished
Second-year students in Manhattan's four-year Electrical Engineering and Computer Engineering programs are introduced to digital circuits in a one-semester 3-credit course ELEC-229. This course includes a laboratory component in which students design and breadboard simple circuits. While the course includes preliminary coverage of VHDL (Very High Speed Integrated Circuits Hardware Description Language), the author believes that an easier introductory language and analysis tool, designed to
more » ... l, designed to parallel the student's progress in learning digital concepts, can help them gain confidence and familiarity with the strengths and weaknesses of digital simulation. The SDL Analyzer described in this paper uses the power of Visual Basic graphics to provide simple logic simulation capabilities for small circuits of the complexity typically found in introductory courses. It is designed as a tutorial aid for students in digital analysis and design courses, and is based on the author's experience teaching the material in the college classroom. Compared with standard VHDL simulators, SDL provides a simpler user interface and reduced capabilities. Students can operate it interactively on their own computers, and study circuit operations step-by-step at their own pace. They can stimulate the circuit interactively, and view the results of analysis, either in tabular form or on the schematic drawn by the analyzer. All results can be saved to disk or printed. This paper describes the SDL language, the SDL analyzer, and includes comparisons of SDL with ABEL and with VHDL, and the author's experiences using SDL in the classroom.
doi:10.18260/1-2--9764 fatcat:dzz6gxbjnzaavfdbmihpcaka3e