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This paper presents a formal approach to verify arithmetic circuits using symbolic computer algebra. Our method describes arithmetic circuits directly with high-level mathematical objects based on weighted number systems and arithmetic formulae. Such circuit description can be effectively verified by polynomial reduction techniques using Gröbner Bases. In this paper, we describe how the symbolic computer algebra can be used to describe and verify arithmetic circuits. The advantageous effects ofdoi:10.1109/iccd.2007.4601876 dblp:conf/iccd/WatanabeHAH07 fatcat:vuxenflrsfgtjjiaq46jlhfmmy